`timescale 1ns/10ps

module div2(clk, reset, start, A, B, D, R, ok, err);
   parameter n = 32;
   parameter m = 16;
   
   input clk, reset, start;
   input [n-1:0] A, B;
   output [n+m-1:0] D;
   output [n-1:0] R;
   output ok, err;
   
   wire invalid, carry, load, run;
   
   div_ctl #(n, m) UCTL(clk, reset, start, invalid, carry, load, run, err, ok);
   div_datapath #(n, m) UDATAPATH(clk, reset, A, B, load, run, invalid, carry, D, R);
   
endmodule

module div_ctl(clk, reset, start, invalid, carry, load, run, err, ok);
   parameter n = 32;
   parameter m = 16;
   parameter STATE_INIT = 3'b001;
   parameter STATE_RUN = 3'b010;
   parameter STATE_FINISH = 3'b100;
   input clk, reset, start, invalid, carry;
   output load, run, err, ok;
   
   reg [2:0] current_state, next_state;
   reg [5:0] cnt;
   reg load, run, err, ok;
    
   always @(posedge clk or negedge reset)
   begin
      if(!reset) begin
         current_state <= STATE_INIT;
         cnt <= 0;
      end else begin
         current_state <= next_state;
         if(run) cnt <= cnt + 1'b1;        
      end
   end
   
   always @(posedge clk or negedge reset)
   begin
      if(!reset) begin
         err <= 0;
      end else if(next_state==STATE_RUN) begin
         if(invalid) err <= 1;        
      end
   end
   
	always @(current_state or start or invalid or carry or cnt)
   begin
      load <= 1'b0;
      ok <= 1'b0;
      run <= 1'b0;
       
      case(current_state)
         STATE_INIT: begin
            if(start) next_state <= STATE_RUN;
            else next_state <= STATE_INIT;
            load <= 1;
         end
         STATE_RUN : begin
            run <= 1;
            if(invalid) begin
               next_state <= STATE_FINISH;   
            end else if(cnt==(n+m-1)) begin
//            end else if(cnt==6'b110000) begin
               next_state <= STATE_FINISH;    
            end else begin
               next_state <= STATE_RUN;
            end
         end
         STATE_FINISH : begin
            ok <= 1;
            next_state <= STATE_FINISH;    
         end
         default : begin
            next_state <= STATE_INIT;    
         end
      endcase
   end   
endmodule

// synopsys translate_off
module DW01_sub(A, B, CI, DIFF, CO);
   parameter n = 32;
   input [n-1:0] A, B;
   input CI;
   output [n-1:0] DIFF;
   output CO;
   
   assign {CO, DIFF} = {1'b0, A} - {1'b0, B} - {{n{1'b0}}, CI};
endmodule
// synopsys translate_on

module div_datapath(clk, reset, A, B, load, run, invalid, carry, D, R);
   parameter n = 32;
   parameter m = 16;
   input clk, reset;
   input [n-1:0] A, B;
   input load, run;
   output invalid, carry;    
   output [n+m-1:0] D;
   output [n-1:0] R;

   reg [n+n+m-2:0] R0;
   reg [n+m-1:0] D;
   reg [n-1:0] B0;
   reg carry;
   
   wire invalid;
   wire [n-1:0] DIFF, R;
   wire CO;

   assign R = {carry, R0[n+n+m-2:n+m]};   
   assign invalid = (B0==0);
   
   DW01_sub #(32) sub(R0[n+n+m-2:n+m-1], B0, 1'b0, DIFF, CO);
   
   always @(posedge clk)
   begin
      if(load) begin
         D <= 0;
         R0 <= {{(n-1){1'b0}}, A, {m{1'b0}}};
         B0 <= B;
         carry <= 1'b0;    
      end else if(run) begin
         if(CO && !carry) begin // A < B
           R0 <= { R0, 1'b0 };
           D <= { D[n+m-2:0], 1'b0 };
           carry <= R0[n+n+m-2];
         end else begin // A >= B
           R0 <= { DIFF, R0[n+m-2:0], 1'b0 };
           D <= { D[n+m-2:0], 1'b1 };
           carry <= DIFF[n-1];
         end
      end
   end
endmodule
